发明名称 PIPELINED A/D CONVERTER
摘要 PROBLEM TO BE SOLVED: To provide a pipelined A/D converter capable of achieving low power consumption while preventing a reduction in feedback factor of an amplifier. SOLUTION: The pipelined A/D converter converts an analog signal to a digital signal, including a plurality of stages connected in cascade connection and an error correction circuit which generates the digital signal, based on sub digital signals respectively outputted from the stages. When a sub digital signal of N bits is outputted in at least one of the stages in the pipelined A/D converter, the stage gain of a transfer function is 2<SP>N-K-1</SP>, the number of returns is 2<SP>N</SP>-2 and an integer K satisfies a relation of 1≤K≤N. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010021918(A) 申请公布日期 2010.01.28
申请号 JP20080182437 申请日期 2008.07.14
申请人 RENESAS TECHNOLOGY CORP 发明人 MORIMOTO YASUO
分类号 H03M1/14 主分类号 H03M1/14
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