| 摘要 |
PURPOSE:To simplify a titled circuit and prevent the circuit system from being influenced by the number of bits of serial data to be inputted. CONSTITUTION:At a time slot 1, a set signal is applied to an input terminal (d) of a delay circuit 41 having a setting function and a reset signal is applied to input terminals (d) of delay circuits 42-45 having reset functions to initialize these cascade delay circuits. When a clock and serial data are applied successively, a leading logical value ''1'' and the succeeding signal indicating series data are propagated to the cascade delay circuits at time slots 2-5. At the time slot 5, the propagated leading logical value ''1'' becomes an output of the final delay circuit 45, so that the data read in the cascade delay circuits are inputted to latch circuits 51-54 in parallel and simultaneously outputted from the latch circuits 51-54 to complete serial-to-parallel conversion. |
