| 发明名称 | Register error protection through binary translation | ||
| 摘要 | Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator. | ||
| 申请公布号 | US9405647(B2) | 申请公布日期 | 2016.08.02 |
| 申请号 | US201113994697 | 申请日期 | 2011.12.30 |
| 申请人 | Intel Corporation | 发明人 | Vera Xavier;Casado Javier Carretero;Monchiero Matteo;Ramirez Tanausu;Herrero Enric |
| 分类号 | G06F11/00;G06F11/263;G06F9/45 | 主分类号 | G06F11/00 |
| 代理机构 | Nicholson De Vos Webster & Elliott LLP | 代理人 | Nicholson De Vos Webster & Elliott LLP |
| 主权项 | 1. A processor comprising: a plurality of registers; an instruction generation logic to generate at least one instruction to read information from at least one register of the plurality of registers in order to detect whether the at least one register of the plurality of registers contains erroneous information; and detection logic to detect at least one register of the plurality registers that is to store information that will not be accessed for longer than a threshold period based, at least in part, on at least a portion of a code being translated by a binary translator. | ||
| 地址 | Santa Clara CA US | ||