Memory control device, semiconductor device, and system board

摘要

According to an embodiment, a memory control device controls a memory from/to which data are read/written by a processor. The memory control device includes a clock switcher and a control signal switcher. The clock receives as input a first clock and a second clock at a higher frequency than the first clock, supplies the first clock to the memory until the second clock becomes stable, and supplies the second clock after the second clock has become stable. The a control signal switcher starts supplying, to the memory, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor while the first clock is being supplied to the memory, and supplies, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.

主权项

1. A memory control device that controls a memory from/to which data are read/written by a processor, the memory control device comprising:
a clock switcher configured to
receive a first clock and a second clock of which clock frequency is higher than that of the first clock, the second clock being a clock generated by a high-frequency oscillator that starts operating in response to an input of an interrupt to the processor,supply the first clock to the memory until the second clock becomes stable, andsupply the second clock to the memory after the second clock has become stable; and a control signal switcher configured to
start supplying, to the memory to which the first clock is being supplied, a first control signal for initializing the memory to a state allowing reading/writing of data by the processor when the interrupt is input to the processor, andsupply, to the memory, a second control signal according to the reading/writing of data by the processor, after the second clock is supplied to the memory and the memory is initialized.