CHARGE TRAPPING NONVOLATILE MEMORY DEVICES, METHODS OF FABRICATING THE SAME, AND METHODS OF OPERATING THE SAME

摘要

A charge trapping nonvolatile memory device includes a source region and a drain region disposed in an upper portion of a substrate and spaced apart from each other by a first trapping region, a channel region, and a second trapping region. A gate stack structure is disposed over the channel region. A first stack including a tunnel insulation layer, a first charge trap layer, and a first blocking insulation layer are disposed over the first trapping region. A second stack including a tunnel insulation layer, a second charge trap layer, and a second blocking insulation layer are disposed over the second trapping region. An interlayer insulation layer is disposed over the substrate and covers the gate stack structure. A first contact plug and a second contact plug penetrate the interlayer insulation layer and respectively contact the source region and the drain region. A third contact plug penetrates the interlayer insulation layer, contacts the gate stack structure, and overlaps with the first and the second charge trap layers.

主权项

1. A charge trapping nonvolatile memory device comprising:
a source region and a drain region disposed in an upper portion of a substrate and spaced apart from each other by a first trapping region, a channel region, and a second trapping region; a gate stack structure disposed over the channel region; a first stack including a tunnel insulation layer, a first charge trap layer, and a first blocking insulation layer disposed over the first trapping region; a second stack including a tunnel insulation layer, a second charge trap layer, and a second blocking insulation layer disposed over the second trapping region; an interlayer insulation layer disposed over the substrate and covering the gate stack structure; a first contact plug and a second contact plug penetrating the interlayer insulation layer and respectively contacting the source region and the drain region; and a third contact plug penetrating the interlayer insulation layer, contacting the gate stack structure and overlapping with the first and the second charge trap layers.