发明名称 TRANSFER SPEED SETTING SYSTEM
摘要 PURPOSE:To check signal speed and adjust the signal speed of an interface automatically to a peripheral equipment by counting a specific code signal from the peripheral equipment by high frequency basic clocks. CONSTITUTION:Before starting operation, a terminal 2 sends a code signal of which only 1 bit is ''1'' to a CPU 1. A counter 5 counts up basic clocks from a high frequency clock generator 4 during the period of ''1'' of the code signal and reports the counted value to the CPU 1. The CPU 1 multiplys the counted value of the counter 5 by the period of the basic clocks ad divides the multiplied value by 1sec to decide transfer clocks. A rate selecting circuit 6 selects a clock with a prescribed speed from a clock generating circuit 12 and sets up data transfer speed at a serial interface 7 so as to be adjuated to that of the terminal 2.
申请公布号 JPS57190445(A) 申请公布日期 1982.11.24
申请号 JP19810076331 申请日期 1981.05.19
申请人 RICOH KK 发明人 ASHIBA YUTAKA
分类号 H04L25/38;G06F13/00;H04L5/14;H04L29/08 主分类号 H04L25/38
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