发明名称 TIMER CIRCUIT
摘要 PURPOSE:To supply an accurate timer signal by adding or deleting a timer signal when the vaue of a counter which counts the timer signal coincides with the output of a switch stored with a previously calculated correction value. CONSTITUTION:An oscillating circuit 1 supplies a clock signal 4 to a CPU3 and a frequency dividing circuit 2. The circuit 2 processes the signal 4 by frequency division to output a timer signal 5. When the period of the signal 5 is, for example, 0.998ms for the 1,000Hz ideal frequency of the signal 5, a correction value 500 is set previously in a switch 8. When a counter 7 counts the signal 5 up to 500, a comparing circuit 9 outputs a strobe signal 10 for coincidence to switch a changeover switch 11 to a gate 12, and while the signal 5 is thinned out before being counted up to 500 and supplied to the CPU13, the counter 7 is reset. When the period of the signal 5 is, for example, 1.002ms, on the other hand, the switch 11 is changed over to the side of a one-shot circuit 13 before the signal 5 is counted up to 500 and one pulse obtained differentiating the leading edge of the output of a circuit 13 through a differentiating circuit 14 is added to supply the resulting signal to the CPU13.
申请公布号 JPS5824236(A) 申请公布日期 1983.02.14
申请号 JP19810122447 申请日期 1981.08.06
申请人 TOKYO SHIBAURA DENKI KK 发明人 MAKINO TETSUO
分类号 H03K17/28;(IPC1-7):03K17/28 主分类号 H03K17/28
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