发明名称 DIGITAL PLL CIRCUIT
摘要 PURPOSE:To reduce power consumption by replacing a part of a ROM to an adder circuit and a phase detection circuit to apply the result to a CMOS LSI easily. CONSTITUTION:An exclusive memory consists of a phase detection circuit PD receiving an output of a latch circuit LAT1 and controlling the output by an output of a one-shot circuit and replacing the latch circuit LAT1 fixing a carry input to a high level and adding the output of the latch circuit LAT1 and the output of the phase detection circuit PD to an adder circuit ADD of the same bit number as that of the circuit LAT1. That is, the titled circuit consists of a one-shot circuit comprising D flip-flops DFF1, DFF2, a NAND gate g1, and an inverter G2 and of a frequency division circuit comprising a 4-bit adder circuit ADD, the 4-bit latch circuit LAT1, the phase detection circuit PD and a D flip-flop DFF3.
申请公布号 JPS6318724(A) 申请公布日期 1988.01.26
申请号 JP19860163005 申请日期 1986.07.10
申请人 NEC CORP 发明人 TAMEGAYA YUKIO
分类号 G11B20/14;H03L7/06 主分类号 G11B20/14
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