| 摘要 |
PURPOSE:To realize an operational amplifier reducing a rising time/falling time. CONSTITUTION:When the gate voltage of P-channel FETs 16, 18 is decreased by an input signal voltage at signal input terminals 101, 102 in a differential amplifier including N-channel FETs 13, 14, the P-channel FETs 11, 12 and a constant current source 15, the voltage of the P-channel FET 19 gets higher and current is supplied from a high level power supply terminal 104 to a signal output terminal 103 via the P-channel FET 18 and then the output voltage rises quickly. On the other hand, when the gate voltage of the P-channel FETs 16, 18 gets higher, the gate voltage of the P-channel FET 19 gets lower, the current supply from the high level power terminal 104 is interrupted and conversely current is supplied to a low level power terminal 105 via the P-channel FET 19, then the voltage at the signal output terminal 103 falls down quickly. Thus, the rising time/falling time are reduced. |
