发明名称 WIRE LAYOUT METHOD
摘要 PURPOSE: To suppress the peak value of noise in such a lattice wiring as power supply wiring by selectively switching the pitch of the lattice wiring which is virtually arranged in a lattice according to the noise occurrence situation. CONSTITUTION: The pitch, namely an electrical length L1 , of a lattice wiring corresponding to modules MOD 1 and MOD2 corresponds to the noise occurrence situation of the modules. That is, after obtaining a noise compression rateαwhere the peak value of noise to be propagated reaches a specific value or less, the pitch is calculated as an electrical length L0 where the noise compression rateαis obtained and the pitch of the lattice wiring corresponding to the module MOD3, namely an electrical length L2 , can also be calculated in a similar manner. Therefore, the electrical lengths become optimized values to fully reduce the peak value of noise at each lattice point of the power supply wiring although the peak value of the noise generated from each module is relatively large and hence fully stabilizing the operation of a large-scale integrated circuit device LSI.
申请公布号 JPH08330523(A) 申请公布日期 1996.12.13
申请号 JP19950159943 申请日期 1995.06.02
申请人 HITACHI LTD 发明人 ITO YUKO;ISOMURA SATORU
分类号 H01L21/822;H01L21/82;H01L27/04;(IPC1-7):H01L27/04 主分类号 H01L21/822
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