| 摘要 |
A clock-controlled latch (140) is provided with an enable input (142) connected between an addressable latch (130) and a relay driver (120), the enable input being connected to a reset signal input (103). A redundancy switch (170) is provided with a reset input (171), a redundancy switching signal input (172), a redundancy switching signal output (174) and an enable output (173). The enable output is connected via an asymmetrical delay line (160) to the enable input (122) of the relay driver (120). The reset input (133) of the addressable latch is connected via a symmetrical delay line (150) to the reset signal input (103).
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