| 摘要 |
PROBLEM TO BE SOLVED: To inhibit the occurrence of a code pattern which is disadvantageous to the reproduction of clocks or the generation of signals by detecting an effective video signal that follows the register value of a scrambler set at a prescribed point of time in a blanking period and setting the most significant register value at 1 when all register value are zero and the next effective video signal is equal to a signal of a certain prescribed code pattern. SOLUTION: When all registers of a scrambler are set at 0 and the input data are equal to one of those data included in prescribed 15 patterns, a control circuit C11 applies the set pulse output to a 1-bit delay circuit C06 via an OR circuit C05 and also applies the clock of an n-multiple clock generation circuit to the most significant circuit C06 to set it at 1. The circuit C06 usually operates with serial clocks but the most significant circuit C06 is set at 1 if the worst pattern is detected. Thus, the data which are disadvantageous to the reproduction of data and clocks are never generated. |
