DIGITAL PLL CIRCUIT AND METHOD FOR CONTROLLING IT

摘要

PROBLEM TO BE SOLVED: To obtain a digital PLL circuit which detects the lead/lag of the phase of a feedback clock from a reference clock by means of a plurality of phase comparing circuits having different phases and generates a clock signal of a prescribed phase by adjusting the delay in a delay circuit at regular time intervals and from which jitters are suppressed by continuously holding the delay in the delay circuit when the detected results of the lead/lag of the phase fall within a prescribed range. SOLUTION: A digital PLL circuit provided with phase comparator circuits 103a-103e is constituted in such a way that a reference clock RCK is inputted to one input of each phase comparator circuit 103a-103e through a three-stage serial least delay circuits 113R and a feedback clock CK1 is inputted to the other input of the phase comparator circuit 103c through a one-stage least delay circuit. Then the output through a two-stage serial least delay circuit is inputted to the other input of the phase comparator circuit 103b and the output through a three-stage least serial delay circuit is inputted to the other input of the phase comparator circuit 103a. In addition, the output through a four-stage serial least delay circuit is inputted to the other input of the phase comparator circuit 103e and the output through a five-stage serial least delay circuit is inputted to the other input of the phase comparator circuit 103e.