| 摘要 |
A circuit for storing and latching defective address data representing an address of a defective portion occurring in a memory cell array of a nonvolatile semiconductor memory device having a redundant function. The circuit includes floating gate field effect transistors and latch circuits. Each floating gate field effect transistor assumes one of a high-threshold state and a low-threshold state, and has a threshold of 0 volts or less (e.g. 0 to -2.5 volts) when in the low-threshold state.
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