| 发明名称 |
Mask set for fabricating integrated circuits and method of fabricating integrated circuits |
| 摘要 |
A mask set is described. In one implementation, the mask set includes: a first plurality of base layer masks, where each base layer mask of the first plurality of base layer masks includes a plurality of base layer tiles of a first tile size; a first plurality of top layer masks, where each top layer mask of the first plurality of top layer masks includes a plurality of first top layer tiles of the first tile size; and a second plurality of top layer masks, where each top layer mask of the second plurality of top layer masks includes a plurality of second top layer tiles of a second tile size; where the second tile size is different from the first tile size. Also, a method of fabricating a plurality of integrated circuits (ICs) is described. |
| 申请公布号 |
US9401281(B1) |
申请公布日期 |
2016.07.26 |
| 申请号 |
US201414281515 |
申请日期 |
2014.05.19 |
| 申请人 |
Altera Corporation |
发明人 |
Plofsky Jordan;Lim Chooi Pei;Biran Danny;Chow Francis Man-Chit |
| 分类号 |
G03F9/00;H01L21/283;H01L21/78;H01L23/544 |
主分类号 |
G03F9/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A mask set comprising:
a first plurality of base layer masks, wherein each base layer mask of the first plurality of base layer masks includes a plurality of base layer tiles of a first tile size; a first plurality of top layer masks, wherein each top layer mask of the first plurality of top layer masks includes a plurality of first top layer tiles of the first tile size; and a second plurality of top layer masks, wherein each top layer mask of the second plurality of top layer masks includes a plurality of second top layer tiles of a second tile size; wherein the second tile size is different from the first tile size. |
| 地址 |
San Jose CA US |
