| 摘要 |
<p>PURPOSE:To produce the signals that can control other circuits (for muting, etc.) by supplying the output signal of a PLL circuit to a delay circuit to sample the ''0'' level side of a clock of the output of the PLL circuit at the rise of the delayed clock of the delay circuit and sampling the ''1'' level side of the clock of the output of the PLL circuit after inverting the delayed clock to detect a clock abnormal position. CONSTITUTION:A D type flip-flop 1 has its output that changes at a drop-out point and is held up to a normal position since the ''0'' level side of the output pulse (b) of a PLL circuit 2 is sampled at the rise of the output pulse loss of a delay circuit 3. While the output of a D type flip-flop 2 changes at a drop-out point and is held up to a normal position since the ''1'' level side of the output pulse of the circuit 2 is sampled at the rise of the output pulse (c) of an inverting circuit 4. These outputs are supplied to a synthesizing circuit 7 and a clock abnormality detecting signal is obtained. This detecting signal is supplied to a voice muting circuit 11, etc.</p> |
