发明名称 ARITHMETIC LOGICAL COMPUTING ELEMENT
摘要 PURPOSE:To improve a speed by providing a selector which inputs the output data of an adder, the output data of a first subtracter and the output data of a second subtracter, selecting and outputting one input in correspondence with the type of designated arithmetic operation. CONSTITUTION:The adder 110 adding first input data X and second input data Y, the first subtracter 131 which sets first input data X to be a minuend and second input data Y to be a subtrahend and the second subtracter 132 which sets first input data X to be the subtrahend and second input data Y to be the minuend are provided. Then, the selector 150 inputting the output of the adder 110, output data of the first subtracter 131 and output data of the second subtracter 132, selecting and outputting one input in correspondence with the type of the designated arithmetic operation is given. Thus, it is not necessary to install the selector in the preceding stage of the adder or the subtracters even if any operation of addition, subtraction and absolute value subtraction is executed.
申请公布号 JPH0443427(A) 申请公布日期 1992.02.13
申请号 JP19900151050 申请日期 1990.06.08
申请人 NEC CORP 发明人 ANDO KOICHI
分类号 G06F7/38;G06F7/50;G06F7/505 主分类号 G06F7/38
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