发明名称 Monteringsarrangemang för ett halvledarelement
摘要 <p>A mounting arrangement is proposed wherein a semiconductor element (10, 50) containing integrated circuitry has solder bumps (20) for electrically coupling the IC to a PCB (40) also comprises a number of further raised members (30) of larger volume than the solder bumps, at least one of which is electrically insulated from the IC. The raised members are solder masses that when heated will reflow only onto designated locations on the PCB. During mounting, the raised member will pull the semiconductor element into correct alignment with the receiving surface, allowing easy automatic mounting of the chip using flip-chip techniques regardless of the arrangement of the connection bumps. The raised members also alleviate the effects of thermal expansion mismatch between the chip and PCB by absorbing the predominant proportion of the resulting stress. A chip scale package is further proposed wherein a carrier (60) is applied to the upper surface of the chip (50) and the raised members are applied to the underside of the carrier.</p>
申请公布号 SE9901781(L) 申请公布日期 2000.11.18
申请号 SE19990001781 申请日期 1999.05.17
申请人 发明人
分类号 H01L21/60;H05K3/30;H05K3/34;(IPC1-7):H01L21/60;H01L23/31 主分类号 H01L21/60
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