| 摘要 |
<P>PROBLEM TO BE SOLVED: To enable a receiving scan latch to release original data, even if the arrival times for the release/capture clocks differ in each clock domain, in data transfer between clock domains. <P>SOLUTION: A plurality of clock domains to each of which a testing clock is supplied from a separate clock generation circuit are provided. In each clock domain, scan latch on the border of the clock domains for receiving an input from another clock domain includes a master latch 30 for latching the input in response to a first clock; a slave latch 32 for latching an output from the master latch in response to a second clock; a selector 34 for supplying a scan input to the master latch, when a mode switchover signal is at a first level and supplying a system input to the master latch, when the signal is at a second level; and a clock control circuit 36 for turning off the first clock, when the mode switchover signal transits from the first level to the second level. <P>COPYRIGHT: (C)2007,JPO&INPIT |
