发明名称 TESTING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To solve the problem it is difficult to confirm whether there is a sufficient time difference between pieces of timing where the output of routes in a competitive relationship is connected to a common later-stage circuit in a normal operation test of a semiconductor integrated circuit. SOLUTION: For a testing method, the operation of the semiconductor integrated circuit 100 including first and second routes and the later-stage circuit is tested while delay larger than that in normal operation is being applied to a route where output should be connected to the later-stage circuit to which the output of the first and second routes is connected earlier in time in the first and second routes including logic circuits 10, 14. Therefore, in a normal test process, it is confirmed whether there is a sufficient time difference between pieces of timing where the output of routes in a competitive relationship is connected to the later-stage circuit. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2010019662(A) 申请公布日期 2010.01.28
申请号 JP20080179889 申请日期 2008.07.10
申请人 NEC ELECTRONICS CORP 发明人 OBATA HIROYUKI
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
代理机构 代理人
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