发明名称 Switching converter
摘要 When a current detection voltage VCS that corresponds to a voltage drop across a detection resistor RCS exceeds a first threshold value VADIM, a current limit comparator asserts a reset pulse. A zero current detection circuit generates a set pulse configured as an instruction to turn on a switching transistor. A logic circuit generates an output pulse S14 according to the reset pulse and the set pulse. When the current detection signal VCS exceeds a second threshold value VTH, a second comparator asserts a comparison signal. An abnormal state detection period is set to a first time period from a time point at which the switching transistor turns on. When the comparison signal is asserted in the abnormal state detection period, an abnormal state detection circuit judges that an abnormal state has occurred.
申请公布号 US9401649(B2) 申请公布日期 2016.07.26
申请号 US201514928374 申请日期 2015.10.30
申请人 ROHM CO., LTD. 发明人 Sasaki Yoshikazu
分类号 H05B33/08;H02M3/335;G02F1/1335 主分类号 H05B33/08
代理机构 Cantor Colburn LLP 代理人 Cantor Colburn LLP
主权项 1. A control circuit for a switching converter, the switching converter comprising: an output capacitor arranged between an input line and an output line; an inductor, a switching transistor, and a detection resistor arranged in series between the output line and a ground line; and a diode having a cathode connected to the input line and an anode connected to a connection node that connects the inductor and the switching transistor, and wherein the control circuit comprises: a first comparator that asserts a reset pulse when a current detection signal that corresponds to a voltage drop across the detection resistor exceeds a first threshold value;a set pulse generator that asserts a set pulse at a timing at which the switching transistor is to be turned on;a logic circuit that receives the set pulse and the reset pulse, and that generates an output pulse such that (i) when the set pulse is asserted, the output pulse is switched to an on level that corresponds to an on state of the switching transistor, and such that (ii) when the reset pulse is asserted, the output pulse is switched to an off level that corresponds to an off state of the switching transistor;a second comparator that asserts a comparison signal when the current detection signal exceeds a second threshold value; andan abnormal state detection circuit that sets an abnormal state detection period to a period from a time point at which the switching transistor turns on up to a time point at which a first time period elapses, and that judges that an abnormal state has occurred when the comparison signal is asserted in the abnormal state detection period.
地址 Ukyo-Ku, Kyoto JP