DEFECT REDUCTION IN III-V SEMICONDUCTOR EPITAXY THROUGH CAPPED HIGH TEMPERATURE ANNEALING

摘要

A structure and method for reducing defects within a III-V compound semiconductor layer grown epitaxially on a mismatched crystalline substrate is provided. The III-V compound semiconductor layer may be surrounded by a thermally stable layer on its sides and a thermally stable capping layer on its upper surface. Subsequent to epitaxial growth, the III-V compound semiconductor layer may be subjected to high temperature annealing in a pressurized atmosphere of the corresponding Group V material present in the III-V compound semiconductor layer. The thermally stable layer and the capping layer may prevent the evaporation of the Group V material from the III-V compound semiconductor layer, as well as cure and rearrange the crystalline lattice structure of the III-V compound semiconductor layer thereby reducing defect density.

主权项

1. A method of protecting an epitaxially grown III-V compound semiconductor layer during high temperature annealing comprising:
forming a thermally stable layer adjacent to and contacting side surfaces of the III-V compound semiconductor layer; and forming a capping layer on an upper surface of the III-V compound semiconductor layer.