MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS

摘要

Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or non-programmable connections in and between levels of the matrix. The connections may couple routing lines to feature cells, groups, rows, blocks, or any other arrangement of components of the pattern-recognition processor.

主权项

1. A device, comprising:
a logical group comprising a plurality of route lines, a first feature cell, and a second feature cell, wherein the first feature cell is configured to transmit an output signal along a first route line of the plurality of route lines to the second feature cell as an input signal to the second feature cell, wherein the first feature cell and the second feature cell of the logical group are separate and distinct from any additional feature cells of any other logical group of the device.