| 摘要 |
A semiconductor memory device including a plurality of memory blocks (1-1, 1-2, 1-3, 1-4) each including a plurality of memory cells (C00, C01, . . . , C31,127). When test data is transmitted from one selected memory cell within each of the memory blocks to one of data bus pairs connected to the memory blocks (DB1, &upbar& D1. . . , DB4, &upbar& D4), all of the test data on the data bus pairs is checked simultaneously by a read test circuit (10). The semiconductor memory device includes first and second power supply terminals and each of the memory blocks having the memory cells arranged in rows and columns. Also included are pairs of data buses, each pair being connected to one of the memory blocks, a cell selection device for selecting one memory cell within each of said memory blocks and connecting the selected memory cells to the corresponding data buses, and a block selection circuit for selecting one pair of the pairs of data buses during a write mode and writing input data into all of the selected memory cells. Further included is a read test circuit connected to the first and second power supply terminals and to the data buses, for detecting the potential of each of the data buses and for checking simultaneously whether the data on the data buses transmitted from the selected memory cells is correct.
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