WIDEBAND DELAY LOCK LOOP CIRCUIT

摘要

PROBLEM TO BE SOLVED: To enable operation over a broad frequency band and to prevent the occurrence of pseudo-clock by providing a loop filter for generating a control signal which adjusts the delay quantity of each delay signal, when the number of leading edges is different from a prescribed number. SOLUTION: A frequency detection logic 12 receives an input reference clock (REF-CK) and a seven-phase clock (CK(1:7)). The logic 12 continuously counts the number of the leading edges of the CK(1:7) within one cycle of the input reference clock and decides whether the phase of each delayed edge is slow or fast, with respect to a reference clock or whether the phase of each delayed edge is in a locked state. In such a case, a pseudo-clock state to another frequency, which is generated in the case a delay time due to the entire delay string is a multiple of a reference clock cycle, is generated. When the number of these leading edges is different from a prescribed number, a loop filter 16 generates a control signal to adjust the delay quantity of each delay element.