| 摘要 |
PROBLEM TO BE SOLVED: To increase the yield of a semiconductor device.SOLUTION: This test circuit has: a test clock terminal for receiving a test clock and provided in a first semiconductor chip; a plurality of clock paths for conveying a test clock from the first semiconductor chip to a second semiconductor chip and disposed between the first semiconductor chip and the second semiconductor chip; a test unit for testing the second semiconductor chip using a test clock and provided in the second semiconductor chip; a clock detection unit for detecting a test clock received via each of the plurality of first clock paths and provided in the second semiconductor chip; and a clock path selection unit, provided in the second semiconductor chip, for selecting a clock path, among the plurality of clock paths, that conveys a test clock detected by the clock detection unit as a test clock path, and supplying a test clock conveyed via the test clock path to the test unit when the second semiconductor chip is tested.SELECTED DRAWING: Figure 1 |
