| 摘要 |
A watchdog timer circuit (40) for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit (30) responsive to receipt of a count clock signal for counting it up, and a timer control circuit (20) which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit (20) interrupts the clock signal counting operation of the timer circuit (30). During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit (20) allows the timer circuit (30) to restart the clock signal counting operation. |
