发明名称 |
PROCESSOR AND METHOD OF CONTROLLING EXECUTION OF PROCESSES |
摘要 |
A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section. |
申请公布号 |
US2016232064(A1) |
申请公布日期 |
2016.08.11 |
申请号 |
US201615133841 |
申请日期 |
2016.04.20 |
申请人 |
Renesas Electronics Corporation |
发明人 |
FUKUDA Kazuhisa |
分类号 |
G06F11/20 |
主分类号 |
G06F11/20 |
代理机构 |
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代理人 |
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主权项 |
1. A multi-processor system comprising:
a first processor; a second processor; a memory circuitry that is shared by the first and second processors, and that stores a first program for the first processor and a second program for the second processor; a first bus coupled to the first processor; and a first detecting circuitry that detects a bus error on the first bus, wherein when the first detecting circuitry detects the bus error, the second processor interrupts a running process for the second program and determines whether to execute either the first program or the second program, and wherein the multi-processor system is included in a single chip. |
地址 |
Tokyo JP |