发明名称 FLIP-FLOP CIRCUIT FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To reduce power consumption without reducing load driving ability and an operation speed, by adding a push-pull type output buffer circuit to the output stage of a flip-flop for an integrated circuit. CONSTITUTION:When the outut Q of a flip-flop circuit 1 has a level H and the Q' has a level L, the loading transistor (TR) T7 of a buffer circuit 4 is turned on and the driving TRT8 is turned off to hold an output terminal 6 at the level H. At this time, a current flowing in the buffer circuit 4 from VCC through the TRs T7 and T8 is substantially zero. A buffer circuit 5 is the same. In driving load capacitors C1 and C2, when the output signals Q and Q' of the circuit 1 have an L to H and an H to L level transition, the level at the output terminal 6 rises up to the level H lagging the rise of the Q. Only during this period, a large current is flowed from the CCC to the C1 through the T7 to charge the C1 in a short time, and in the other time, a fine current is flowed.
申请公布号 JPS5836019(A) 申请公布日期 1983.03.02
申请号 JP19810133358 申请日期 1981.08.27
申请人 FUJITSU KK 发明人 TAKAHASHI HIROMASA;NISHIUCHI KOUICHI;NAKAMURA TETSUO;MATSUMURA NOBUTAKE;HOSHIKAWA RIYUUSUKE
分类号 H03K3/356;(IPC1-7):03K3/356 主分类号 H03K3/356
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