| 摘要 |
PURPOSE:To shorten the access time of a control memory used for obtaining a micro instruction so as to shorten a machine time and to improve performance by reading previously an instruction command at an address next to the instruction command read out by an instruction register. CONSTITUTION:In an instruction fetching cycle, the output of an address register 2 addresses a buffer memory 1, and the instruction command is read and set to the instruction register 6. Simultaneously the output of the register 2 is increased by one by a positive one adder 3 to address the memory 1, and some part of the instruction command to be processed next time is read out and set to an address register 4. When the next instruction fetching cycle starts after instruction processing at an address A, the instruction command at an address (A+1) is set to the register 6 from the memory 1. Simultaneously the address set to the register 4 in the previous instruction fetching cycle indexes a control memory 5, and the micro instruction for instruction processing is set to a micro instruction register 7. |
