摘要 |
An analog-to-digital converter (ADC) for telecommunication applications such as ASDL/VDSL UMTS/GPRS wherein the conversion is realized in current mode instead of voltage mode. The power consumption is thereby reduced and the converter is adapted to be used in (low voltage) battery operated products. The structure of the converter is also simplified because summing of currents is easier than summing of voltages. The converter comprises at least a first set of N = 64 first curre nt cells (CC) coupled in parallel between lines (L+, L-) of a differential current bus. Each first current cell comprises a current source (ICC) to supply a fir st additional current (64xlref) to the current bus under control of first comparator circuits (COMP1+, COMP1-). The first comparator circuits of the current cell s are coupled in cascade and activated step-by-step one after each other. In a preferred embodiment, the converter (ADC) further includes one or more second set of N second current cells (FC) also coupled in parallel between the lines (L+, L-) of the differential current bus and similar to th e first current cells. The second cells however include an amplifier (AMP2+, AMP2-) with a gain N coupled between the lines and second comparator circuits (COMP2+, COMP2-), and have a second current source (IFC) to supply a second additional current (Iref) to the current bus under control of the second comparator means. Moreover, the second current cells are activated (F2) afte r the operation of the first current cells of the first set is completed. The amount of hardware is thereby reduced, e.g. by factor of 2 5, as well as the cost owing to a smaller silicon area on the chip.
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