发明名称 FORMATION OF INTERLAYER INTERCONNECTION IN MULTILAYER-STRUCTURED ELEMENT
摘要 PURPOSE:To eliminate the yield of stress due to the difference in thermal expansion coefficients between an interlayer interconnection and a device layer, by epitaxially growing a conductive compound semiconductor selectively on a conductor layer so as to bury a through-hole, and forming the interlayer interconnection in the through- hole part. CONSTITUTION:An N-type active layer 2 is formed in the surface part of a substrate 1. Electrodes 4 are formed on the surface of the active layer 2. An SrF2 layer 5 is evaporated on the entire surface of the substrate 1 as a seed layer. An SiO2 film 6 is selectively formed furthermore. Thereafter, a Ge layer 7 is evaporated and formed on the SiO2 film 6 and on the SrF2 layer 5 at the surrounding part of the film 6. The Ge layer 7 on the SiO2 film is recrystallized. A GaAs layer 8 is laminated on the entire surface. A through-hole 9 is formed in the GaAs layer 8 and the SrF2 layer 5 at an interconnection forming part 3 on the active layer 2. Then, an interlayer interconnection 10 is formed on the active layer 2 in the first layer device, which is exposed to the bottom part of the through-hole 9 so as to bury the through-hole 9. Thus the thermal expansion coefficients of the interlayer interconnection and the surrounding device layer are made to agree, and a large amount of stress is not yielded between both parts.
申请公布号 JPS62193148(A) 申请公布日期 1987.08.25
申请号 JP19860032842 申请日期 1986.02.19
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 YAMAGISHI NAGAYASU;KIMURA TAMOTSU;KAWARADA YOSHIHIRO
分类号 H01L23/52;H01L21/3205;H01L27/00;H01L27/095;H01L29/80 主分类号 H01L23/52
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