发明名称 PROGRAMMABLE COUNTER
摘要 <p>PURPOSE:To reduce the amount of hardware by incorporating a clock oscillator, which supplies an input clock signal, in a counter device and making it unnecessary for an output clock to be provided with an external device of a clock supply source of the clock before frequency division. CONSTITUTION:When a chip select signal 10 is inputted to a counter device 2 and a control signal is inputted onto a control bus 6, a control logic circuit 13 turns on an internal control signal 16 and data on a data bus 5 is transferred from a data bus buffer 12 to a frequency division ratio setting circuit 14. The circuit 14 sets a frequency division ratio by this data and outputs a frequency division ratio control signal 17 to a counter 15. Since an oscillator 18 always outputs a clock 19 having a fixed frequency while power is supplied to the device 2, the counter 15 divides the frequency of this clock 19 by the signal 17 and outputs an output clock 9. The frequency division ratio is arbitrarily set by writing data to be set to the circuit 14 from the external. Thus, the external device of the clock supply source of the clock before frequency division is unnecessary for the output clock to reduce the amount of hardware.</p>
申请公布号 JPH01307817(A) 申请公布日期 1989.12.12
申请号 JP19880139919 申请日期 1988.06.07
申请人 MITSUBISHI ELECTRIC CORP 发明人 AKITA YASUTAKA
分类号 G06F1/04;G06F1/08 主分类号 G06F1/04
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