| 摘要 |
<p>A pulse signal delay circuit comprises an input node (IN) for receiving a first pulse signal (P1), an output node (OUT) for outputting a second pulse signal (P3), a delay circuit (2) for delaying the first pulse signal (P1) to provide a delayed signal, a first comparator (5) for comparing the first pulse signal (P1) with the second pulse signal (P3) to output a first comparison result, and a second comparator (3) for comparing the first comparison result with the delayed signal to output a second comparison result.</p> |
