发明名称 DATA WRITEEIN AND READOUT SYSTEM FOR MICROCOMPUTER
摘要 <p>PURPOSE:To reduce the number of RAMs, by using RAM at page mode, sequentially writing in the data of one word with split at write-in, and taking one word through the synthesis of the data sequentially read out at readout. CONSTITUTION:The microcomputer of bit system N is taken as the 8-bit system and RAM1-4 of 16K-wordX1-bit are used to constitute the screen RAM of TV game machine. The RAM1-4 are provided with the address input terminal in 7- bit, CPU address signal and TV scanning signal are output with switching with the CPU/TV switching signal at the address selector 5 for output, the address signal switches the row address and column address, and the page address, and RAM1-4 are accessed by the row address in 7-bit, column address in 6-bit and page address in 1-bit. Further, the data D0-D3, D4-D6 input with the data selector 6 are selected to input them to RAM1-4 and the input data are latched at the data latch circuit 7.</p>
申请公布号 JPS5616254(A) 申请公布日期 1981.02.17
申请号 JP19790091364 申请日期 1979.07.18
申请人 UNIVERSAL KK 发明人 HAMADA NORIHIKO
分类号 G06F12/02;G06F12/04;G06F13/00;G06F15/78 主分类号 G06F12/02
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