Out-of-order processing with operation bumping to reduce pipeline delay

摘要

A superscalar microprocessor (200) includes a scheduler (280) which stores information related to operations and issues operations for out-of-order execution by execution units (251 to 257). Operations are issued without regard for the availability of operands required for execution. After the issue stage, an operand forward stage identifies operand sources which may be a register file (290) or an operation in the scheduler (280). The scheduler (280) forwards a value and state information for the operand. The state information indicates whether an operation providing the operand was or is being completed so that execution can continue. The state information can also indicate a wait until a source operation is completed. If the wait is too long, the issued operation is bumped so that another operation can be issued and executed. This reduces hold ups and increases utilization of execution units (251 to 257).