| 摘要 |
PROBLEM TO BE SOLVED: To synchronize a node synchronizing signal without communication synchronized information by outputting the node synchronizing signal which is locked by means of the phase lock signal of a specified frequency obtained by frequency-diving a communication clock signal. SOLUTION: In a master 1 provided with a communicatioin interface 2 for transmitting digital data to a digital communication PLL system and a slave 11 provided with the communication interface 12 for receiving digital data from the system, the communication interfaces 2 and 12 are connected by a communication cable 20 and a bus time indicating common time information is held. In the interface 2, a clock generating circuit generates the bus time and a bus timer frequency dividing circuit 9 frequency-divides a communication clock signal so as generate the phase lock signal of the frequency by which the frequeny of the communication clock signal and also the frequency of the node synchronizing signal are divided. Then, PLL(phase synchronizing loop) 4 outputs the node synchronizing signal where the phase is locked by the phase lock signal. |
