| 摘要 |
PROBLEM TO BE SOLVED: To stabilize operation when restored especially from a power down mode and a clock suspend-mode of an internal clock generating section incorporated in a synchronous DRAM and the like, and also to stabilize operation of the synchronous DRAM and the like. SOLUTION: A command control clock generating 1c CSPG of an internal clock generating section of a synchronous DRAM and the like is constituted basically of N channel MOSFET N41, in which drain is coupled to an internal node n1 and an input clock signal CCIN is inputted to its gate, a N channel MOSFET N42 provided between a source of the MOSFET N42 and a ground potential VSS, and P channel MOSFET P41 provided between power source voltage VDD and the internal node n1. Internal pulse signals TRN2E and TRN 1EB the generating timing of which are optimized respectively and independently are supplied respectively to gates of the MOSFET N42 and P41.
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