| 摘要 |
A receiving apparatus includes a counter for counting for a prescribed period of time the number of bits having one of two different levels, out of bits forming a digital signal which is entered and having the two different levels, and supplying a count signal, a bit rate detector for calculating the bit rate of the digital signal from the count signal and supplying a multiplying factor selection signal, a differentiating circuit, into which the input digital signal is entered, for supplying a pulse signal at a varying point of the input digital signal, a rectifying circuit for accomplishing full-wave rectification of the pulse signal, and supplying a rectified pulse signal, a band-pass filter for passing harmonics of the clock component of the input digital signal contained in the rectified pulse signal, and a frequency dividing circuit, into which the harmonics are entered, for frequency-dividing the harmonics by a ratio set on the basis of the multiplying factor selection signal, and supplying a resultant frequency-divided clock signal. |
