| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a burn-in stress control circuit of a semiconductor memory device to reduce a peak current applied to a memory cell array. SOLUTION: A burn-in stress control circuit has a logic gate 35 which outputs reverse signals of burn-in enable(PWBE) signals, a capacitor 43 which relieves the rising curve of the PWBE signal with a resistor 37, a 1st transistor 31 whose control terminal is connected to the other end of the resistor 37, whose 1st main electrode is connected to a power supply voltage and which is turned on only when the level of the PWBE signal is logic-high and outputs the power supply voltage from its 2nd main electrode and a 2nd transistor 33 whose control terminal is connected to the output terminal of the logic gate 35, whose 1st main electrode is connected to the ground voltage, whose 2nd main electrode is connected to the 2nd main electrode of the 1st transistor and which is turned on only when the level of the PWBE signal is logic-low. With this constitution, a peak current applied to a memory cell array and noises are reduced.</p> |
