MEMORY CONTROLLER, MEMORY CONTROL METHOD AND IMAGE GENERATING DEVICE

摘要

PROBLEM TO BE SOLVED: To efficiently access a memory. SOLUTION: In a timing generation circuit 27T, addresses of a same row are generated and further, plural column addresses on the row are sequentially generated. The row addresses and column addresses are supplied to DRAMCELL 28D through ROWDEC 28Y and RADDEC 28R respectively. The column addresses are also supplied to a column address buffer 28C, and are delayed by a fixed time interval before being supplied to DRAMCELL 28D via WADDEC 28W. Reading access of data to DRAMCELL 27D through a read data bus 44 and writing access of an arithmetic result by an arithmetic processing circuit 27E are executed simultaneously.