| 摘要 |
PURPOSE: An apparatus for interfacing UTOPIA(Universal Test and Operation PHY Interface for ATM) level1 device with a UTOPIA level2 device in an ATM exchange is provided to implement active/standby FIFO(First-In-First-Out) to two FIFOs to simultaneously perform a cell reading and a PHY address polling, and to perform a data bus matching in a UTOPIA level2 emulation circuit, so as to interface the UTOPIA level1 device with the UTOPIA level2 device. CONSTITUTION: A FIFO memory block is composed of at least two FIFO memories(30a,30b) and implement different queues. An FIFO selector(20) decides where cells read from UTOPIA level1 device(10) have to be recorded of the two FIFO memories(30a,30b). A UTOPIA level2 emulation circuit(40) reads cells recorded in the FIFO memory block to transmit the read cells to a UTOPIA level2 device(50), and simultaneously latches a PHY address relating to a next cell from the FIFO memory block, then responds to a PHY address polling relating to the next cell requested by the UTOPIA level2 device(50).
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