| 摘要 |
PURPOSE: A wafer pattern structure is provided to reduce the number of inferior semiconductor devices by preventing a semiconductor chip pattern and an alignment mark pattern from being damaged in a semiconductor fabrication process. CONSTITUTION: A wafer pattern structure includes semiconductor chip area(1) and alignment mark areas. The alignment mark area(5) includes a first area, a second area and a prohibition area. Many semiconductor chip areas includes many semiconductor chip patterns. Alignment mark patterns for arranging a wafer during a light-exposing process are formed in the alignment mask area. The first area includes the alignment mark pattern. A second area includes a damage prevention pattern of a predetermined shape to prevent a damage of the alignment mark pattern during the etching process after the light-exposing process. The prohibition area is determined between the alignment mark pattern and the damage prevention pattern. Thereby, the wafer pattern structure reduces the number of inferior semiconductor devices by preventing a semiconductor chip pattern and an alignment mark pattern from being damaged in a semiconductor fabrication process.
|
