发明名称 Digital-to-analog converter using different multiplicators between first and second portions of a data holding period
摘要 It is object to provide a digital-to-analog converter capable of generating an output waveform having less distortion without increasing the operating speed of components. A D/A converter comprises four D flip-flops 10-1 through 10-4, four multipliers 12-1 through 12-4, three adders 14-1 through 14-3, a D/A converter 16, and two integrating circuits 18-1 and 18-2. Input data is fed sequentially to the four D flip-flops and held therein. The multiplier multiplies the data held in the respective D flip-flops by different multiplicators in the first half and second half of one clock period and the multiplication results are added by the three adders. A stepwise analog voltage corresponding to the sum is generated by the D/A converter 16 and integrated twice by means of the two integrating circuits 18-1 and 18-2.
申请公布号 US6486814(B2) 申请公布日期 2002.11.26
申请号 US20010890519 申请日期 2001.07.31
申请人 SAKAI YASUE 发明人 KOYANAGI YUKIO
分类号 H03M1/66;H03M3/02;(IPC1-7):H03M1/66 主分类号 H03M1/66
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