发明名称 DELAY CIRCUIT AND METHOD FOR TESTING THE CIRCUIT
摘要 <p>Operation of a delay circuit is switched by a signal for selecting normal operation and test operation, and when operation of the delay circuit is switched to the normal operation, a signal is transmitted to a normal operation output with a time lag set by a normal operation input. When operation of the delay circuit is switched to the test operation, a test operation loop is formed by inverting the output of the delay circuit and an oscillation waveform dependent on the time lag is outputted. The output is counted by a counting circuit as the number dependent on the time lag.</p>
申请公布号 WO2008114307(A1) 申请公布日期 2008.09.25
申请号 WO2007JP00232 申请日期 2007.03.16
申请人 OKAMOTO, KOJI;FUJITSU LIMITED 发明人 OKAMOTO, KOJI
分类号 H03K5/13;G01R31/28 主分类号 H03K5/13
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