发明名称 |
Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems |
摘要 |
An interface mechanism (10) between two processors, such as a host processor (70) and a processor (31) in an intelligent controller (30) for mass storage devices (40), and utilizing a set of data structures employing a dedicated communications region (80A) in host memory (80). Interprocessor commands and responses are communicated as packets over an I/O bus (60) of the host (70), to and from the communication region (80A), through a pair of ring-type queues (80D) and (80E). The entry of each ring location (e.g., 132, 134, 136, 138) points to another location in the communications region where a command or response is placed. The filling and emptying of ring entries (132-138) is controlled through the use of an 'ownership' byte or bit (278) associated with each entry. The ownership bit (278) is placed in a first state when the message source (70 or 31) has filled the entry and in a second state when the entry has been emptied. Each processor keeps track of the rings' status, to prevent the sending of more messages than the rings can hold. These rings permit each processor to operate at its own speed, without creating race conditions and obviate the need for hardware interlock capability on the I/O bus (60).
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申请公布号 |
US4449182(A) |
申请公布日期 |
1984.05.15 |
申请号 |
US19810308826 |
申请日期 |
1981.10.05 |
申请人 |
DIGITAL EQUIPMENT CORPORATION |
发明人 |
RUBINSON, BARRY L.;GARDNER, EDWARD A.;GRACE, WILLIAM A.;LARY, RICHARD F.;KECK, DALE R. |
分类号 |
G06F15/16;G06F5/06;G06F9/445;G06F9/52;G06F12/00;G06F13/12;G06F13/20;G06F13/38;G06F15/167;G06F15/173;G06F15/177;H04L13/08;(IPC1-7):G06F9/46 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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