| 摘要 |
<p>PURPOSE:To reduce the space and cost by synthesizing and detecting plural reference signals depending on the difference of level so as to decrease the number of signal transmission lines than the number of reference signals. CONSTITUTION:A basic clock signal (a) from a basic clock generating circuit 1 and an operating clock signal (b) from a clock generating circuit 2 are inputted respectively by transistors (TR)5a, 5b of a reference signal output circuit 5. When the reference clock signal (a) and the operating clock signal (b) are at high level, since level difference is generated with an output signal of an output circuit 5, they are synthesized and become a reference operation signal (c). The signal (c) is inputted to a level detection circuit 6, the level of the signal (c) is detected depending on the difference of inverters 6a, 6b and the signals are divided into the original reference signal.</p> |
