| 摘要 |
An input CMOS inverter comprises a complementary pair of first and second MOS transistors having their gates connected together to receive an input signal, and a buffer circuit connected between drains of the first and second MOS transistors. The buffer circuit is preferably an analog switch circuit having a complementary pair of third and fourth MOS transistors responsive to the input signal and connected in parallel. In response to a potential variation caused at the drain of one of the first and second transistors, the buffer circuit causes a potential variation at the drain of the other transistor after a delay. There is provided a second MOS inverter having a complementary pair of fifth and sixth MOS transistors with their gates connected to the drains of the first and second transistors, respectively. A feedback circuit is connected to the output of the second inverter to suppress the potential variation at the drains of the first and second transistors. The feedback circuit preferably includes a third inverter and a complementary pair of seventh and eighth MOS transistors connected to the drains of the first and second transistors, respectively, and controlled by the third inverter.
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