发明名称 ARITHMETIC UNIT FOR TAG ARCHITECTURE
摘要 PURPOSE:To couple a tag and a data field in a single machine cycle by providing internally a logic circuit which receives information including a tag value, information including the data field, and tag and field designating information as inputs and couples them logically to generate data with the tag. CONSTITUTION:AND circuit 6 operates AND at every 4 bits of a tag word 2 and those of a field mask 4, and an AND circuit 7 operates AND between 4 bits of a data word 3 and those of the field mask 4 inverted by a NOT circuit 8. Consequently, the output 9 of the AND circuit 6 has the tag value in a higher order N-bit position and has all '0' in a lower order N'-bit position, and the output 10 of the AND circuit 7 has the data field in the lower order N'-bit position and has all '0' in the higher order N-bit position. An OR circuit 11 operates OR at every bit of the output 9 of the AND circuit 6 and that of the output 10 of the AND circuit 7. As the result, data 5 with the tag which has the tag value in the higher order N-bit position and has the data field in the lower order N'-bit position is obtained as the output of the OR circuit 11.
申请公布号 JPS62182920(A) 申请公布日期 1987.08.11
申请号 JP19860023998 申请日期 1986.02.07
申请人 HITACHI LTD 发明人 NOJIRI TORU;YASUDA HAJIME;KAWASAKI SHUNPEI
分类号 G06F9/44;G06F7/00 主分类号 G06F9/44
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