发明名称 ERROR DETECTION SYSTEM FOR DIGITAL CODE TRANSMISSION SYSTEM
摘要 PURPOSE:To detect a code error caused over twice by transmitting the number information bits in a frame representing a prescribed logic value as number information and allowing the reception side to collate additionally the said information and the number of information bits counted. CONSTITUTION:A number accumulation counter 15 counting the accumulated number of 1s or 0s in the information bits in the frame of a transmission input 11, a frame counter 13, a number information seat designation circuit 12 designating a seat inserted with the number information counted by the number accumulation counter 15 and a number information insertion circuit 14 inserting the number information counted by the counter 15 into the frame based on the output of the circuit 12 are provided to the sender side. A frame synchronizing circuit 22, a number accumulating counter 23 counting the accumulated number of 1s or 0s of the information bit in the frame of the reception input 21, a number information read circuit 24 and an exclusive OR circuit 25 collating outputs of the counter 23 and the read circuit 24 are provided to the receiving side.
申请公布号 JPS62264740(A) 申请公布日期 1987.11.17
申请号 JP19860108880 申请日期 1986.05.12
申请人 NEC CORP 发明人 MATSUMOTO KOJI
分类号 H04L1/00 主分类号 H04L1/00
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